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1 ps9056a 07/12/11 features ? 4-lane, 1:2 mux/demux that will support 2.7gbps or 1.62gbps dp rev 1.1a signals ? 1-channel 1:2 mux/demux for dp_hpd signal ? 1-diferential channel 1:2 mux/demux for dp_aux signal ? insertion loss for high speed channels @ 2.7 gbps: -1.5db ? -3db bandwidth for high speed channels of 3.25 ghz ? low bit-to-bit skew , 7ps max (between '+' and '-' bits) ? low crosstalk for high speed channels: -33db@2.7 gbps ? low of isolation for high speed channels: -26db@2.7 gbps ? v dd operating range: 3.3v 10% ? esd tolerance: +/-8kv contact on ports a and b per iec61000-4-2 specifcation ? low channel-to-channel skew, 35ps max ? packaging (pb-free & green): - 56 tqfn (zfe) - 42 tqfn (zhe) description pericom semiconductors pi3vdp612-a mux/demux is targeted for next generation digital video signals. tis device can be used to connect a displayport? source to two independent display- port sinks or to connect two displayport sources to a single dp display. te newly released displayport spec requires a data rate of 2.7 gbps with ac coupled i/os. pericom's solution has been specif- cally designed around this standard and will support such sig- nals. application routing of displayport signals with low signal attenuation be- tween source and sink. block diagram pin description - 56-pin d0+ d0 d1+ d1 d2+ d2- d3+ d3- aux+ aux - hpd cab_det/led d0+a d0 -a d1+a d1 -a d0+b d0-b d1+b d1-b d2+a d2-a d3+a d3-a d2+b d2-b d3+b d3-b sel1 - - logic control sel2 aux+ a aux- a hpd a cab_deta/leda aux+ b aux- b hpd b cab_detb/ledb aux_sel aux_sel d0+ d0- d1+ d1- v dd d2+ d2- d3+ d3- gnd aux+ aux- hpd cab_det/led gnd vdd sel1 sel2 gnd gnd d2+a d2-a d3+a d3-a d0+b d0-b d1+b d1-b d2+b d2-b d3+b d3-b gnd vdd aux+a aux-a hpd_a cab_det/leda gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 gnd v dd d0+ a d0- a d1+a d1-a v dd gnd gnd v dd cab_det/ledb hpd_b aux-b aux+b v dd gnd 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 gnd pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching 11-0103
2 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching pin description - 42-pin d0+a d0+ d0- d1+ d1- aux_sel d2+ d2- d3+ d3- vdd aux+ aux- hpd cab_det/led sel1 sel2 d2+a d2-a d3+a d3-a d0+b d0-b d1+b d1-b d2+b d2-b d3+b d3-b vdd aux+a aux-a hpd_ a cab_deta/led_a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 d0-a vdd d1- a d1+ a cab_detb/led_b aux+b aux-b hpd_b 18 19 20 21 42 41 40 39 gnd 11-0103
3 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching pin description 42-package pin # 56-package pin # pin name signal type description esd 2 1 aux_sel input logic control for aux signals: if low then aux from com port will connect to aux from port a. if high, then aux from com port will connect to aux from port b. 3 2 d0+ i/o positive lane0 signal for common port +/-7kv 4 3 d0- i/o negative lane0 signal for common port +/-7kv 5 4 d1+ i/o positive lane1 signal for common port +/-7kv 6 5 d1- i/o negative lane1 signal for common port +/-7kv 15, 26, 39 6, 17, 22, 27, 34, 50, 55 v dd power 3.3v power supply 7 7 d2+ i/o positive lane2 signal for common port +/-7kv 8 8 d2- i/o negative lane2 signal for common port +/-7kv 9 9 d3+ i/o positive lane3 signal for common port +/-7kv 10 10 d3- i/o negative lane3 signal for common port +/-7kv *gnd plate 11, 16, 20, 21, 28, 29, 35, 48, 49, 56 gnd ground ground 11 12 aux+ i/o positive aux signal for common port +/-8kv 12 13 aux- i/o negative aux signal for common port +/-8kv 13 14 hpd i/o hpd for common port +/-8kv 14 15 cab_det/led i/o common port pin for cable detect signal or led common port +/-8kv 16 18 sel1 input port selection control. if low, then port a is ac- tive. if high, then port b is active 17 19 sel2 input port selection control for hpd path and cab_ det/led path only: if low, then port a is active. if high, then port b is active. 20 gnd power ground 21 gnd power ground 22 v dd power 3.3v power supply 18 23 cab_detb/ ledb i/o port b pin13 from dual mode dp connector or led from port b +/-8kv 19 24 hpd_b i/o hpd for port b +/-8kv 20 25 aux-b i/o negative aux signal for port b +/-8kv 21 26 aux+b i/o positive aux signal for port b +/-8kv (continued) 11-0103
4 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching 42-package pin # 56-package pin # pin name signal type description esd 22 30 cab_deta/ leda i/o port a cable detect from dual mode dp connector or led from port a +/-8kv 23 31 hpd_a i/o hpd for port a +/-8kv 24 32 aux-a i/o negative aux signal for port a +/-8kv 25 33 aux+a i/o positive aux signal for port a +/-8kv 27 36 d3-b i/o negative lane3 signal for port b +/-8kv 28 37 d3+b i/o positive lane3 signal for port b +/-8kv 29 38 d2-b i/o negative lane2 signal for port b +/-8kv 30 39 d2+b i/o positive lane2 signal for port b +/-8kv 31 40 d1-b i/o negative lane1 signal for port b +/-8kv 32 41 d1+b i/o positive lane1 signal for port b +/-8kv 33 42 d0-b i/o negative lane0 signal for port b +/-8kv 34 43 d0+b i/o positive lane0 signal for port b +/-8kv 35 44 d3-a i/o negative lane3 signal for port a +/-8kv 36 45 d3+a i/o positive lane3 signal for port a +/-8kv 37 46 d2-a i/o negative lane2 signal for port a +/-8kv 38 47 d2+a i/o positive lane2 signal for port a +/-8kv 40 51 d1-a i/o negative lane1 signal for port a +/-8kv 41 52 d1+a i/o positive lane1 signal for port a +/-8kv 42 53 d0-a i/o negative lane0 signal for port a +/-8kv 1 54 d0+a i/o positive lane0 signal for port a +/-8kv truth table (sel control) function sel 1/sel2/aux_sel port a is active l port b is active h notes: sel1 is only for dp lanes sel2 is only for hpd/cab_det signals aux_sel is only for aux path pin description 11-0103
5 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching storage temperature ....................................................C65c to +150c supply voltage to ground potential ................................C0.5v to +3.6v dc input voltage .............................................................. C0.7v to 3.6v dc output current ....................................................................... 120ma power dissipation ........................................................................... 0.5w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. expo - sure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) dc electrical characteristics for switching over operating range (t a = C40c to +85c, v dd = 3.3v 10%) parameter description test conditions (1) min typ (1) max units v ih input high voltage guaranteed high level 1.6 v v il input low voltage guaranteed low level 0.75 v ik clamp diode voltage v dd = max., i in = C18ma C0.7 C1.2 i ih input high current v dd = max., v in = v dd 5 a i il input low current v dd = max., v in = gnd 5 i off i/o leakage when part is of v dd = 0v, v input = 0v to 3.6v 50 r on on resistance between input to output v dd = 3.0v, -0.6v 6 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching fig 1. crosstalk setup fig 2. of-isolation setup + ? + ? balanced port1 dut + ? 50 50 + ? balanced port2 50 50 + ? + ? balanced port1 balanced port2 dut + ? 50 50 + ? + ? balanced port1 balanced port2 dut fig 3. diferential insertion loss 11-0103
7 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching fig 4. crosstalk fig 4. xtalk 11-0103
8 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching fig 5. of isolation 11-0103
9 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching fig 6. insertion loss 11-0103
10 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching (ohms) 20.0 ron 2.00/div 0.00 0.00 vin (v) 200.m /div 3.00 fig 7. ron curve for high speed signal path only (dx ) 11-0103
11 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching switching characteristics (t a = -40o to +85oc, v dd = 3.3v10%) parameter description min. max. units t pzh , t pzl line enable time 0.5 15.0 ns t phz , t plz line disable time 0.5 15.0 t pd propagation delay (input pin to output pin) 200 ps t b-b bit-to-bit skew within the same diferential pair 7 ps t ch-ch channel-to-channel skew 50 ps r t 4pf c l v dd v in v out 200-ohm 200-ohm 6.0v pulse generator d.u.t test circuit for electrical characteristics(1-5) notes: 1. c l = load capacitance: includes jig and probe capacitance. 2. r t = termination resistance: should be equal to z out of the pulse generator 3. output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. all input impulses are supplied by generators having the following characteristics: prr mhz, z o = 50?, t r 2.5ns, t f 2.5ns. 5. the outputs are measured one at a time with one transition per measurement. switch positions test switch t plz , t pzl (output on b-side) 6.0v t phz , t pzh (output on b-side) gnd prop delay open switching waveforms voltage waveforms enable and disable times t plz v dd /2 v dd /2 v dd v oh 0v v ol v dd/2 v dd/2 t phz t pzl t pzh output 1 output 2 v ol v oh sel v ol + 0.3v v oh ? 0.3v 11-0103
12 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching test circuit for dynamic electrical characteristics pi3vdp12412 hp11667a agilent n5230a 300khz-20ghz pna-l network analyzer application section - pre-emphasis waveforms input pre-emphasis = 9.5db; red waveform is input of pi3vdp612-a & black is output of pi3vdp612-a 11-0103
13 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching input pre-emphasis = 6db; red waveform is input of pi3vdp612-a and black is output of pi3vdp612-a 11-0103
14 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching input pre-emphasis = 3.5db; red waveform is input of pi3vdp612-a & black is output of pi3vdp612-a 11-0103
15 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching packaging mechanical: 56-contact tqfn (zf) 1 description: 56-contact, thin fine pitch quad flat no-lead (tqfn) package code: zf56 document control #: pd-2024 revision: c date: 05/15/08 08-0208 note: ? for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 11-0103
16 ps9056a 07/12/11 pi3vdp612-a 4-lane displayport? rev 1.1a compliant switch with triple control logic for fast switching ordering information ordering code package code package description pi3vdp612-azfe zf pb-free & green, 56-contact tqfn PI3VDP612-AZHE zh pb-free & green, 42-contact tqfn notes: ? thermal characteristics can be found on the company web site at www .pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com packaging mechanical: 42-pin tqfn (zh) 1 description: 42-contact thin fine pitch quad flat no-lead (tqfn) package code: zh (zh42) document control #: pd-2035 revision: c date: 02/17/09 notes: 1. all dimensions are in millimeters, angles in degrees. 2. coplanarity applies to the exposed thermal pad as well as the terminals. 3. refer jedec mo-220 4. recommended land pattern is for reference only. 5. thermal pad soldering area 09-0116 displayport is a trademark of vesa www.vesa.org note: ? for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 11-0103

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